Hands-on lab: assertion based verification
Technology Park Ljubljana and WEDASoft are organising an international course Hands-on LAB on Assertion Based Verification.
Technology Park Ljubljana and WEDASoft are organising an international course Hands-on LAB on Assertion Based Verification with Neil Rattray, Application Engineer supporting Mentor's line of Functional Verification Projects.
Throughout this course, which will take place on 25 November 2010 at congress centre Therme Olimia, extensive hands-on lab exercises provide participant with practical experience using either ModelSim DE or Questa software. The labs use either VHDL or Verilog designs (at the choice of the attendee).
In this course participants will learn how ABV can help to become more productive in system level verification and debug of design. A detailed overview on what assertions are and how they should be applied to design will be given. Also covered are the specific language features in SystemVerilog that enable to define the assertions and properties and how to bind them to the design. During the training will also learn how to use ModelSim DE or Questa to simulate a design using SVA and how we can leverage this to verify or enhance the functional coverage of design.
- FPGA/ASIC Design Engineers
- Verification Engineers
- VHDL or Verilog experience
General & specific Information
This event is a cooperation between Technology Park Ljubljana and WEDASoft. The content is based on the technologies provided by Mentor Graphics. Training computers are provided by WEDASoft for the duration of the event. Lunch and coffee breaks are included.
Number of participants is strictly limited to maximum 10 attendees total (max 2 per company). The event is with cost - details are available in the application form.
Registration is obligatory and only possible by using the application form.
Application deadline is on October 31st 2010.
Technology Park Ljubljana